A memory cell of a nonvolatile semiconductor memory device has a transistor structure in which a gate insulating layer and a control gate electrode are deposited on a semiconductor substrate. Writing/erasing is performed for the memory cell by applying a voltage between the control gate electrode and the substrate to cause a tunneling current to flow, and by controlling a threshold voltage in accordance with charge amount in a charge storage layer. Examples of the structure of the memory cell include a metal-oxide-nitride-oxide-silicon (MONOS) structure and a stack gate structure.
The MONOS structure and the like are also referred to as a charge trap type. The charge trap type is formed by sequentially depositing, for example, a tunneling insulating layer (silicon oxide layer) as a gate insulating layer to selectively pass charges through, a charge storage insulating layer (silicon nitride layer), and a blocking insulating layer (silicon oxide layer) to block a current between the charge storage insulating layer and the control gate electrode. The charge trap type changes a threshold by trapping charges into trap sites locally existing in the silicon nitride layer.
The stack gate structure is also referred to as a floating gate type. The floating gate type is formed by sequentially depositing a tunneling insulating layer (silicon oxide layer), a floating gate electrode (polysilicon layer), an intergate insulating layer (ONO layer), and a control gate electrode, for example. Writing/erasing is performed by applying a high voltage between the control gate electrode and the semiconductor substrate to cause an FN (Fowler-Nordheim) tunneling current to flow, and by transferring charges between the tunneling insulating layer and the floating gate electrode. In other words, data is stored by controlling a threshold voltage in accordance with the charge amount within the floating gate electrode.
A memory cell of each of these types is selected by a select transistor adjacent to the memory cell. The select transistor does not need to continue storing charges. In the select transistor, for example, a gate insulating layer (silicon oxide layer) and a control gate electrode (polysilicon layer) are sequentially deposited.
It is important that a threshold voltage of the memory cell transistor and that of the select transistor should be within tolerance.
Japanese Patent Application Publication No. 2008-159614 discloses a floating gate type structure as follows. A memory cell transistor includes a floating gate electrode, an intergate insulating layer formed on the floating gate electrode, and a control gate electrode formed on the intergate insulating layer. A select transistor includes a lower side gate electrode, an intergate insulating layer formed on the lower side gate electrode and having an opening, a blocking layer formed at least in the opening and having a function to block diffusion of metal atoms, and an upper side gate electrode formed on a second intergate insulating layer and electrically connected to the lower side gate electrode through the blocking layer. The control gate electrode of the memory cell transistor and the upper side gate electrode of the select transistor are fully silicided.
The disclosed floating gate type has a configuration in which the lower gate electrode of the select transistor has polysilicon left unsilicided, and the control gate electrode of the memory cell transistor is fully silicided. The gate electrodes of the memory cell transistor and the select transistor can have work functions different from each other. The floating gate type makes use of the configuration in which these gate electrodes share the intergate insulating layer and in which the select transistor has the opening in the intergate insulating layer.
However, the charge trap type has no structure in which the intergate insulating layer is formed. Accordingly, it is difficult to directly apply the disclosed technique of the stack gate structure to the charge trap type. Additionally, the disclosed technique has no option but to control a threshold voltage by leaving polysilicon unsilicided in the lower side gate electrode of the select transistor, and thus has difficulty in employing another configuration.